The present invention relates to an apparatus and method for implementing bus locking in computer systems having mixed types of architecture.
Bus locking is used in computer systems having multiple processors in order to synchronize transactions among the processors. The synchronization is required so that two or more processors do not access the corresponding bus at the same time for certain transactions, which may cause data corruption in the system or malfunctioning of the attempted transactions. In traditional bus locking, the processors use a register in order to identify whether any of the processors have requested a lock on the bus. If one of the processors has locked the bus, as identified by a status of the register, the other processors refrain from issuing transactions on the bus until the status of the register indicates unlocking of the bus. Therefore, in order to synchronize the processors, as one processor performs a locked transaction all other processors are locked out of the bus. The processor performs the transaction and then resets the register, permitting other processors in the system to access the bus.
Some systems having multiple processors permit multiple access to a bus through a process referred to as pipelining or cache line locking. In this type of system, the processors use a built-in protocol when issuing transactions on the bus. Therefore, the system uses the protocol to properly maintain and execute transactions issued on the bus by multiple processors.
Since the protocol synchronizes the transactions, bus locking is not necessary in those systems. Therefore, the systems using cache line locking typically do not support bus locking. Certain applications operating on processors within such a multi-processor system, however, use the traditional bus locking rather than the cache line locking method. If that application attempts a locked transaction, it will be unable to obtain a lock on the bus. Accordingly, the system must either accommodate both traditional bus locking and cache line locking or only run applications using cache line locking. Limiting the system to cache line locking applications may significantly limit the versatility of the system, and in some situations it may not be possible or practical to limit the applications in that manner.
Accordingly, the need exists for an apparatus and method to accommodate bus line locking and cache line locking in a system having a mixed architecture.
A method consistent with the present invention permits locked transactions within a computer system interfacing processors on a first bus that supports bus locking with a second bus that does not support bus locking. The method includes detecting via the first bus an indication of a request for a locked transaction requiring a shared resource in the system, and obtaining the resource required for the transaction. When the resource is obtained, an indication of the locked transaction is signaled to the processors in the system to quiesce the system, and the locked transaction is sent via the second bus for execution. When the locked transaction completes, the resource is relinquished to allow future locked transactions.
An apparatus consistent with the present invention permits locked transactions within a computer system interfacing processors on a first bus that supports bus locking with a second bus that does not support bus locking. The apparatus detects via the first bus an indication of a request for a locked transaction requiring a shared resource in the system, and it obtains the resource required for the transaction. When the resource is obtained, the apparatus signals to the processors in the system an indication of the locked transaction to quiesce the system and sends via the second bus the locked transaction for execution. When the locked transaction completes, the resource is relinquished to allow future locked transactions.